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/usr/src/linux-oracle-headers-5.15.0-1040/arch/x86/include/asm/   drwxr-xr-x
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/* SPDX-License-Identifier: GPL-2.0 */
/*
 * AMD SEV header common between the guest and the hypervisor.
 *
 * Author: Brijesh Singh <[email protected]>
 */

#ifndef __ASM_X86_SEV_COMMON_H
#define __ASM_X86_SEV_COMMON_H

#define GHCB_MSR_INFO_POS        0
#define GHCB_DATA_LOW            12
#define GHCB_MSR_INFO_MASK        (BIT_ULL(GHCB_DATA_LOW) - 1)

#define GHCB_DATA(v)            \
    (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)

/* SEV Information Request/Response */
#define GHCB_MSR_SEV_INFO_RESP        0x001
#define GHCB_MSR_SEV_INFO_REQ        0x002
#define GHCB_MSR_VER_MAX_POS        48
#define GHCB_MSR_VER_MAX_MASK        0xffff
#define GHCB_MSR_VER_MIN_POS        32
#define GHCB_MSR_VER_MIN_MASK        0xffff
#define GHCB_MSR_CBIT_POS        24
#define GHCB_MSR_CBIT_MASK        0xff
#define GHCB_MSR_SEV_INFO(_max, _min, _cbit)                \
    ((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) |    \
     (((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) |    \
     (((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) |    \
     GHCB_MSR_SEV_INFO_RESP)
#define GHCB_MSR_INFO(v)        ((v) & 0xfffUL)
#define GHCB_MSR_PROTO_MAX(v)        (((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK)
#define GHCB_MSR_PROTO_MIN(v)        (((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK)

/* CPUID Request/Response */
#define GHCB_MSR_CPUID_REQ        0x004
#define GHCB_MSR_CPUID_RESP        0x005
#define GHCB_MSR_CPUID_FUNC_POS        32
#define GHCB_MSR_CPUID_FUNC_MASK    0xffffffff
#define GHCB_MSR_CPUID_VALUE_POS    32
#define GHCB_MSR_CPUID_VALUE_MASK    0xffffffff
#define GHCB_MSR_CPUID_REG_POS        30
#define GHCB_MSR_CPUID_REG_MASK        0x3
#define GHCB_CPUID_REQ_EAX        0
#define GHCB_CPUID_REQ_EBX        1
#define GHCB_CPUID_REQ_ECX        2
#define GHCB_CPUID_REQ_EDX        3
#define GHCB_CPUID_REQ(fn, reg)        \
        (GHCB_MSR_CPUID_REQ | \
        (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \
        (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS))

/* AP Reset Hold */
#define GHCB_MSR_AP_RESET_HOLD_REQ        0x006
#define GHCB_MSR_AP_RESET_HOLD_RESP        0x007

/* GHCB Hypervisor Feature Request/Response */
#define GHCB_MSR_HV_FT_REQ            0x080
#define GHCB_MSR_HV_FT_RESP            0x081

#define GHCB_MSR_TERM_REQ        0x100
#define GHCB_MSR_TERM_REASON_SET_POS    12
#define GHCB_MSR_TERM_REASON_SET_MASK    0xf
#define GHCB_MSR_TERM_REASON_POS    16
#define GHCB_MSR_TERM_REASON_MASK    0xff
#define GHCB_SEV_TERM_REASON(reason_set, reason_val)                          \
    (((((u64)reason_set) &  GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \
    ((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS))

#define GHCB_SEV_ES_REASON_GENERAL_REQUEST    0
#define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED    1

#define GHCB_RESP_CODE(v)        ((v) & GHCB_MSR_INFO_MASK)

#endif

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