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/* SPDX-License-Identifier: GPL-2.0 */
#ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H
#define DT_BINDINGS_MEMORY_TEGRA20_MC_H

#define TEGRA20_MC_RESET_AVPC        0
#define TEGRA20_MC_RESET_DC        1
#define TEGRA20_MC_RESET_DCB        2
#define TEGRA20_MC_RESET_EPP        3
#define TEGRA20_MC_RESET_2D        4
#define TEGRA20_MC_RESET_HC        5
#define TEGRA20_MC_RESET_ISP        6
#define TEGRA20_MC_RESET_MPCORE        7
#define TEGRA20_MC_RESET_MPEA        8
#define TEGRA20_MC_RESET_MPEB        9
#define TEGRA20_MC_RESET_MPEC        10
#define TEGRA20_MC_RESET_3D        11
#define TEGRA20_MC_RESET_PPCS        12
#define TEGRA20_MC_RESET_VDE        13
#define TEGRA20_MC_RESET_VI        14

#define TEGRA20_MC_DISPLAY0A        0
#define TEGRA20_MC_DISPLAY0AB        1
#define TEGRA20_MC_DISPLAY0B        2
#define TEGRA20_MC_DISPLAY0BB        3
#define TEGRA20_MC_DISPLAY0C        4
#define TEGRA20_MC_DISPLAY0CB        5
#define TEGRA20_MC_DISPLAY1B        6
#define TEGRA20_MC_DISPLAY1BB        7
#define TEGRA20_MC_EPPUP        8
#define TEGRA20_MC_G2PR            9
#define TEGRA20_MC_G2SR            10
#define TEGRA20_MC_MPEUNIFBR        11
#define TEGRA20_MC_VIRUV        12
#define TEGRA20_MC_AVPCARM7R        13
#define TEGRA20_MC_DISPLAYHC        14
#define TEGRA20_MC_DISPLAYHCB        15
#define TEGRA20_MC_FDCDRD        16
#define TEGRA20_MC_G2DR            17
#define TEGRA20_MC_HOST1XDMAR        18
#define TEGRA20_MC_HOST1XR        19
#define TEGRA20_MC_IDXSRD        20
#define TEGRA20_MC_MPCORER        21
#define TEGRA20_MC_MPE_IPRED        22
#define TEGRA20_MC_MPEAMEMRD        23
#define TEGRA20_MC_MPECSRD        24
#define TEGRA20_MC_PPCSAHBDMAR        25
#define TEGRA20_MC_PPCSAHBSLVR        26
#define TEGRA20_MC_TEXSRD        27
#define TEGRA20_MC_VDEBSEVR        28
#define TEGRA20_MC_VDEMBER        29
#define TEGRA20_MC_VDEMCER        30
#define TEGRA20_MC_VDETPER        31
#define TEGRA20_MC_EPPU            32
#define TEGRA20_MC_EPPV            33
#define TEGRA20_MC_EPPY            34
#define TEGRA20_MC_MPEUNIFBW        35
#define TEGRA20_MC_VIWSB        36
#define TEGRA20_MC_VIWU            37
#define TEGRA20_MC_VIWV            38
#define TEGRA20_MC_VIWY            39
#define TEGRA20_MC_G2DW            40
#define TEGRA20_MC_AVPCARM7W        41
#define TEGRA20_MC_FDCDWR        42
#define TEGRA20_MC_HOST1XW        43
#define TEGRA20_MC_ISPW            44
#define TEGRA20_MC_MPCOREW        45
#define TEGRA20_MC_MPECSWR        46
#define TEGRA20_MC_PPCSAHBDMAW        47
#define TEGRA20_MC_PPCSAHBSLVW        48
#define TEGRA20_MC_VDEBSEVW        49
#define TEGRA20_MC_VDEMBEW        50
#define TEGRA20_MC_VDETPMW        51

#endif

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